1. Field of the Invention
This invention relates to a matrix circuit capable of manufacturing with integrated circuits and decreasing the area occupying the surface of a semiconductor chip.
2. Description of the Prior Art
Although the number of the operation steps of a table type electronic computer or the like is generally different depending upon the operation function thereof, 64, 128, 256 and 512 steps are used in most cases. In the case of a computer, the term step is used to mean an address representing a calculating operation. Thus, the steps are addresses that determine the operations to be performed in respective steps. For example, the setting of an operand is made in the first step, the set operand is entered in an operational register in the second step, the operand is set in the third step, and so on.
In a memory device, the steps correspond to addresses that determines the informations to be stored. For the sake of description, a 512 step control gate, or a read only memory device (ROM) will be taken as an example of the matrix circuit.
As shown in FIG. 1, a control gate (ROM) having 512 steps has been constructed to produce 512 outputs by decoding 2.sup.9 control signals or a control signal having 9 inputs and to use 512 outputs as the control signals for performing desired calculating operations. Assuming now that 24 control signals are necessary for a desired operation, a matrix circuit or a ROM is constituted by 512 input conductors arranged in the direction of Y axis and 24 output conductors arranged in the direction of X axis as shown in FIG. 1. Suppose now that wired OR gate circuits (gate circuits constituted by P channel field effect transistors) are used to constitute the ROM, that a grounded conductor is commonly used for two output conductors as shown in FIG. 2, and that each field effect transistor comprises an aluminum gate (although a polysilicon gate can also be used). With the ROM of this construction, when one bit has a dimension of 24 .mu. .times. 28 .mu., a pattern of the ROM as shown in FIG. 3 will be obtained. Since a = 48 .mu., and b = 28 .mu., the dimension in the direction of Y axis is 28 .mu. .times. 512 = 14336 .mu. and that in the direction of X axis is 48 .mu. .times. 24/2 = 576 .mu.. Although the area occupied by the ROM is about 8.258 mm.sup.2, the dimension in the direction of Y axis is extremely large, that is 14336 .mu., thus rendering it difficult to fabricate the circuit with integrated circuits by mass production technique.
Many efforts have been made to make equal or comparable as far as possible the lengths of the sides of the matrix circuit. According to one approach, 9 inputs of the 512 step ROM described above is divided into 3 inputs and 6 inputs, namely 8 steps and 64 steps, and 8 OR gate circuits are used to obtain one output. FIG. 4 is a diagram showing one example of the ROM according to this method. FIG. 5a shows the detail of the circuit for one output, and FIG. 5b shows a portion of the circuit pattern. In this construction, the ROM operates to obtain the product between an 8 step control signal and a 64 step control signal and so that the output has 512 steps which is sufficient to produce desired control signals. The reason for this will be described hereunder by taking 32 steps as an example.
In FIG. 6 which corresponds in principle to FIG. 1, suppose now that an output O.sub.1 is expressed by the following equation:
O.sub.1 = 12.multidot.13.multidot.14.multidot.15 = 12+13+14+15 = abcde + abcde + abcde + abcde (1)
output O.sub.1 can be modified as follows 2)
O.sub.1 = CDE(AB + AB + AB + AB) (2)
accordingly, decoders respectively having two inputs A and B, and three inputs C, D and E may be used to form required logical operations by a ROM. FIG. 7 shows such a ROM and the detail of the circuit thereof is shown in FIG. 8. Thus,
O.sub.1 = (3' + 0) (3' + 1) (3' + 2) (3' + 3) = 3'.multidot.0 + 3'.multidot.1 + 3'.multidot.2 + 3'.multidot.3 = 3'(0 + 1 + 2 + 3) (3)
since 3' = CDE, 0 = AB, 1 = AB, 2 = AB and 3 = AB, equation (3) can be rewritten as follows
O.sub.1 = CDE(AB + AB + AB + AB) (4)
thus, equation (3) is identical to equation (2).
Output O.sub.2 can be expressed similarly. Thus, in FIG. 6
o.sub.2 = 0.multidot.13.multidot.22.multidot.27 = 0 + 13 + 22 + 27 = abcde + abcde + abcde + abcde (5)
in FIG. 7
o.sub.2 = (0' + 0) (3' + 1) (5' + 2) (6' + 3) = 0.multidot.0' + 1.multidot.3' + 2.multidot.5' + 3.multidot.6' = abcde + abcde + abcde + abcde (6)
it will be clear that equation (6) is identical to equation (5).
Output O.sub.3 can be expressed similarly. Thus in FIG. 6
o.sub.3 = 1.multidot.2.multidot.3.multidot.4.multidot.5.multidot.6.multidot.7.m ultidot.13.multidot.14.multidot.15.multidot.16.multidot.17.multidot.18 .multidot.19.multidot.20.multidot.21.multidot.23.multidot.24.multidot. 25.multidot.27.multidot.28.multidot.29.multidot.30.multidot.31.multido t.
= 1+2+3+4+5+6+7+13+14+15+16+17+18+19+20+21+23+24+25+27+28+29+30+31
hence
O.sub.3 = ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE (7)
in FIG. 7
o.sub.3 = (1.multidot.4'.multidot.5'.multidot.6'.multidot.7'+0) (0'.multidot.1'.multidot.3'.multidot.4'.multidot.5'.multidot.6'.multi dot.7'.multidot.+1) .times. (0'.multidot.1'.multidot.3'.multidot.4'.multidot.7'+2) (0'.multidot.1'.multidot.3'.multidot.4'.multidot.5'.multidot.6'.multi dot.7'+3)
= (1'+4'+5'+6'+7').multidot. 0+(0'+1'+3'+4'+5'+6'+ )] 1+(0'+1'+3'+4'+7').multidot. 2+(0'+1'+3'+4'+5'+6'+7').multidot. 3
hence
O.sub.3 = ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE (8)
again equation (8) is identical to equation (7). In the above equations,
______________________________________ -0' = --C .multidot. --D .multidot. --E 0' = --C .multidot. --D .multidot. --E -1' = C .multidot. --D .multidot. E 1' = C .multidot. --D .multidot. --E -2' = --C .multidot. D .multidot. --E 2' = --C .multidot. D .multidot. --E -3' = C .multidot. D .multidot. --E 3' = C .multidot. D .multidot. --E -4' = --C .multidot. --D .multidot. E 4' = --C .multidot. --D .multidot. E -5' = C .multidot. --D .multidot. E 5' = C .multidot. --D .multidot. E -6' = --C .multidot. D .multidot. E 6' = --C .multidot. D .multidot. E -7' = C .multidot. D .multidot. E 7' = C .multidot. D .multidot. E ______________________________________
Thus it will be clear that a ROM having 2.sup.5 inputs (32 steps) may be constructed either as shown in FIG. 6 or FIG. 7.
However, in the case of a ROM shown in FIGS. 4 and 5, there are 24 .times. 8 = 192 signals in the direction of X axis and 8 + 64 = 72 signals in the direction of Y axis. Accordingly, when a pattern is prepared according to the design standard described above, the dimention in the direction of X axis becomes 48 .mu. .times. (102/2) = 4608 .mu. and that in the direction of Y axis becomes 28 .mu. .times. 64 + 12 .mu. .times. 8 = 1888 .mu., thus giving an occupation area of the ROM of about 8,7 mm.sup.2 which is slightly larger than that of the prior example. However, as the lengths in the direction of X and Y axies are decreased whereby this arrangement is suitable for assembling the ROM with integrated circuits. However, in the ROM for use in a computer or the like, such peripheral circuits-control flip-flop circuits are often formed on a single semiconductor chip together with the elements described above. In this example too, since decoders are also formed, the ROM having a dimension of 4.608 mm .times. 1.888 mm requires an excessively large occupation area thus decreasing the productivity and increasing the manufacturing cost. This is caused by the fact that one grounded lines is commonly used for two output lines of the ROM with the result that the number of the grounded lines increases in proportion to the number of the output lines, thus increasing the percentage of the occupation area of the grounded lines.